In electronic design automation, a floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional blocks. In modern electronic design process, floorplans are created during the floorplanning stage, which is an early stage in the hierarchical approach to chip design. Floorplanning takes into account some of the geometrical constraints in a design, including for example the location of bonding pads for off-chip connections.
It would be advantageous to implement flip-flops and other integrated circuitry in a 3D format. A 3D semiconductor device (or stacked IC device) can contain two or more semiconductor devices stacked vertically so they occupy less space than two or more conventionally arranged semiconductor devices. The stacked IC device is a single integrated circuit built by stacking silicon wafers and/or ICs and interconnecting them vertically so that they behave as a single device.
Conventionally, the stacked semiconductor devices are wired together using input/output ports either at the perimeter of the device or across the area of the device or both. The input/output ports slightly increase the length and width of the assembly. In some new 3D stacks, through-silicon vias (TSVs) completely or partly replace edge wiring by creating vertical connections through the body of the semiconductor device. By using TSV technology, stacked IC devices can pack a great deal of functionality into a small footprint. This TSV technique is sometimes also referred to as TSS (Through Silicon Stacking).
Device scaling and interconnect performance mismatch has increased exponentially (i.e., up to 50× for global and up to 163× for local interconnects) and is expected to continue to increase even further. This exponential increase in device and interconnect performance mismatch has forced designers to use techniques such as heavy buffering of global interconnects which subsequently has increased chip area and power. Current 3D methodologies only try to assemble 2D blocks into 3D stacks. This approach only helps to reduce the inter-block nets, if applicable, and does not leverage the 3D-IC within the blocks and further improvements are left on the table. The following two references disclose known 3D block-level TSV planning and 3D floorplanning of 2D blocks, respectively: D. H. Kim, R. O. Topaloglu and S. K. Lim, “Block-Level 3D IC Design with Through-Silicon-Via Planning”, Proc. ASPDAC, 2011, pp. 335-340; and J. Knechtel, I. Markov and J. Lienig, “Assembling 2-D Blocks Into Chips”, IEEE Trans. On CAD, 2012, pp. 228-241.
Accordingly, there is a need for systems and methods to improve the capabilities of 3D designs, thereby minimizing wirelength and improving the overall power/performance envelope of the 3D design.